The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs) also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. Indeed, most ICs are complementary MOS (CMOS) circuits that use both P channel MOS (PMOS) transistors and N channel (NMOS) transistors.
The trend in IC fabrication is to incorporate more and more circuitry on a single IC chip and to simultaneously improve the performance of the circuit. To achieve the performance goals, manufacturers have turned to techniques that apply strain to the individual transistors. Properly applied strain can be used to increase the mobility of majority carriers (holes for a PMOS transistor and electrons for an NMOS transistor) in the channel of the MOS transistors. One way to provide the proper strain is to form dual stress layers (DSL), sometimes also called “dual stress liners” overlying the transistors. Tensile stress layers are formed over NMOS transistors and compressive stress layers are formed over PMOS transistors. Further improvements in performance can be achieved by reducing time delays by reducing contact resistance, for example between source or drain regions and associated interconnect metallization. Contact resistance can be reduced by forming metal silicide contacts on the source and drain regions. Unfortunately the combination of dual stress layers and metal silicide contacts has led to a significant morphological degradation of the metal silicide which manifests itself as voids in the metal silicide. These voids can lead to significant yield reduction.
Accordingly, it is desirable to provide high yield methods for fabricating integrated circuits that incorporate dual stress layers. In addition, it is desirable to provide methods for fabricating CMOS integrated circuits that incorporate DSL and metal silicide contacts. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.